Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs

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概要

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• Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0%and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks.

• 2010-12-01

著者

• Jia Xiaomin

  National Laboratory For Parallel And Distributed Processing School Of Computer National University O

• LU Pingjing

  National Laboratory for Parallel and Distributed Processing, School of Computer, National University of Defense Technology

• SUN Caixia

  National Laboratory for Parallel and Distributed Processing, School of Computer, National University of Defense Technology

• ZHANG Minxuan

  National Laboratory for Parallel and Distributed Processing, School of Computer, National University of Defense Technology

• Sun Caixia

  National Laboratory For Parallel And Distributed Processing School Of Computer National University Of Defense Technology

• Lu Pingjing

  National Laboratory For Parallel And Distributed Processing School Of Computer National University Of Defense Technology

• Zhang Minxuan

  National Lab. For Parallel And Distributed Processing School Of Computer National Univ. Of Defense Technol.

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