VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

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概要

• 論文の詳細を見る

• In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

• （社）電子情報通信学会の論文
• 2009-09-01

著者

• Li Kang

  School Of Electronic Engineering University Of Electronic Science And Technology Of China

• LI Jian

  School of Public Health, Kunming Medical University

• Li Jian

  School Of Electronic Engineering University Of Electronic Science And Technology Of China

• YU Juebang

  School of Electronic Engineering, University of Electronic Science and Technology of China

• Yu Juebang

  School Of Electronic Engineering University Of Electronic Science And Technology Of China

• Li Jian

  School Of Chemistry And Chemical Engineering Shandong University

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