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Vlsi Design And Education Center (vdec) The University Of Tokyo | 論文
- Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks
- LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
- 7-(2-Aminomethyl-1-azetidinyl)-4-oxoquinoline-3-carboxylic Acids as Potent Antibacterial Agents : Design, Synthesis, and Antibacterial Activity
- Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
- Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks(Power Optimization)(VLSI Design and CAD Algorithms)
- Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
- A System Level Optimization Techinique for Application Specific Low Power Memories(Special Section on VLSI Design and CAD Algorithms)
- Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
- Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
- The use of single-shot explosive welding technique for the fabrication of aluminum/stainless steel composites
- Single-Shot Explosive Welding of Hard-to-Weld JIS A5083/SUS304 Clad Using SUS304 Intermediate Plate
- A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate(Special Section on Papers Selected from ITC-CSCC 2000)
- Multi-Level Bounded Model Checking with Symbolic Counterexamples
- A Unified Framework for Equivalence Verification of Datapath Oriented Applications
- An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences(Simulation and Verification, VLSI Design and CAD Algorithms)
- A 0.18-μm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- A Basic Framework for Event-Based Monitoring by Networked Smart Image Sensors (特集 画像の認識と理解)