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STMicroelectronics | 論文
- Full-Wave Analysis of Power Distribution Networks in Printed Circuit Boards
- A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below
- CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications
- Highly Manufacturable and Cost-effective Single Ta_xC / Hf_xZr_O_2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond
- Si_Ge_x/Si Selective Etch with HCl for Thin Si-Channel Transistors Integration
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
- Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
- A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels : A High Co-Integration Potential
- Analytical model for subband engineering in undoped double gate MOSFETs
- Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications
- Full-Chip Implementation of IDEALSmile on 90-nm-Node Devices by ArF Lithography
- 65nm Device Manufacture Using Shaped E-Beam Lithography
- Improvement of Bulk CMOS Electrostatic Integrity using Germanium and Carbon co-implantation
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
- Nano-CMOS & Emerging Technologies - Myths and Hopes
- Is a "Power Optimized" Roadmap Realistic for High Performance Applications?
- Impact of Tunnel Etching Process on Electrical Performances of SON Devices
- A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method