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National Asic Research Center Southeast University | 論文
- A Modified BP Algorithm for LDPC Decoding Based on Minimum Mean Square Error Criterion
- Duty Cycle Corrector for Pipelined ADC with Low Added Jitter
- An 11.2-mW 5-GHz CMOS Frequency Synthesizer with Low Power Prescaler for Zigbee Application
- A CMOS voltage controlled oscillator topology for suppression of flicker noise up-conversion
- A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks