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Mitsubishi Electric Corp. Itami‐shi Jpn | 論文
- A Hierarchical Global Router for Macro-Block-Embedded Sea-of-Gates (Special Section on VLSI Design and CAD Algorithms)
- Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
- A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
- A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs (Special Issue on New Architecture LSIs)
- A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI
- AlGaAs High-Power Laser Diode with Window-Mirror Structure by Intermixing of Multi-Quantum Well for CD-R(Special Issue on Recent Progress in Semiconductor Lasers and Light-Emitting Devices)
- Millimeter-Wave Monolithic AlGaAs/InGaAs/GaAs Pseudomorphic HEMT Low Noise Amplifier Modules for Advanced Microwave Scanning Radiometer
- Simulation of Dopant Redistribution During Gate Oxidation Including Transient-Enhanced Diffusion Caused by Implantation Damage
- A Synchronization Scheme for Packet Mode MIMO-OFDM Signals in Wireless LAN(Terrestrial Radio Communications)
- A Scheme to Evaluate Cell Throughput of Multi-Rate Wireless LAN Systems with CSMA/CA(Wireless Communication Technology)
- Temperature Dependence of Gain Characteristics in 1.3-μm AlGaInAs/InP Strained Multiple-Quantum-Well Semiconductor Lasers (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
- Temperature Dependence of Gain Characteristics in 1.3-μm AlGaInAs/InP Strained Multiple-Quantum-Well Semiconductor Lasers (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
- Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits (Special lssue on SISPAD'99)
- 2-Dimensional Simulation of FN Current Suppression Including Phonon Assisted Tunneling Model in Silicon Dioxide
- 3-D Topography and Impurity Integrated Process Simulator (3-D MIPS) and Its Applications (Special Issue on TCAD for Semiconductor Industries)
- A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- A 28 mW 16-bit Digital Signal Processor for the PDC Half-Rate CODEC (Special Issue on Low-Power LSI Technologies)
- A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
- Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation(the IEEE International Conference on SISPAD '02)
- An L-Band High Efficiency and Low Distortion Multi-Stage Amplifier Using Self Phase Distortion Compensation Technique(Special Issue on Low-Distortion, High-Power, High-Efficiency Active Device and Circuit Technology)