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Department of Electronics Engineering, The University of Tokyo | 論文

• Multi-Level Bounded Model Checking with Symbolic Counterexamples
• Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
• Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
• Multi-Level Bounded Model Checking with Symbolic Counterexamples
• Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture
• Performance Estimation with Automatic False-Path Detection for System-Level Designs

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