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Department of Communications and Computer Engineering, Kyoto University | 論文
- Special Section on VLSI Design and CAD Algorithms
- Manufacturability-Aware Design of Standard Cells(Physical Design,VLSI Design and CAD Algorithms)
- Unruptured pseudoaneurysm of the cystic artery with acute calculous cholecystitis incidentally detected by computed tomography
- Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
- Statistical Gate Delay Model for Multiple Input Switching
- Timing Analysis Considering Temporal Supply Voltage Fluctuation
- Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
- An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
- Large Photoinduced Refractive Index Change of Polymer Films Containing and Bearing Norbornadiene Groups and Its Application to Submicron-Scale Refractive-Index Patterning
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Hepatocellular Carcinoma in a Patient with Primary Biliary Cirrhosis and Seronegativity for Markers of Hepatitis B Virus and Hepatitis C Virus : Report of a Case
- Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)
- Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
- Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
- Increase in Delay Uncertainty by Performance Optimization(Special Section on VLSI Design and CAD Algorithms)
- Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
- Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(VLSI Design and CAD Algorithms)
- Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)