Shimatani Tamio | Dept. Of Machine Intelligence And System Engineering Intelligent System Design Laboratory Tohoku Uni
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- 同名の論文著者
- Dept. Of Machine Intelligence And System Engineering Intelligent System Design Laboratory Tohoku Uniの論文著者
Dept. Of Machine Intelligence And System Engineering Intelligent System Design Laboratory Tohoku Uni | 論文
- New Electrically-Thinned Intrinsic-Channel SOI MOSFET with 0.01μm Channel Length
- Investigation of Non-Equilibrium Carrier Transport in Sub-0.1μm MOSFET's Based on Monte Carlo Analysis
- A New Three-Dimensional Multiport Memory for Shared Memory in High Performance Parallel Processor System
- Three-Diensional Integration Technology Based on Wafer Bonding Technique Using Micro-Bumps
- New MOS Current Mode Logic Using SOI-MOSFET with Body Terminal