北川 隆司 | 広島大・大学院理
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概要
論文 | ランダム
- A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation
- Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL
- 160 Gbit/s clock recovery with electro-optical PLL using bidirectionally operated electroabsorption modularor as phase comparator
- An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
- A false-lock-free clock/data recovery PLL for NRZ data using adaptive phase frequency detector